From Java code to Verilog?

Question

I'm trying to write a small java program that is capable of producing Verilog code. As I hardly know the Verilog language, I have problems creating a simple example.

Let's assume we have 2 inputs a, b , and 1 output c . Also 2 states. State1 is the initial state, and goes to State2 for a certain condition wire1 , which requires b = 1 .

My output in this example would have state2 & a as condition to be met.

Question: Using the approximate design below, how would the full Verilog code look according to my example?

//simplified without inheritance
class Input {
    String varname;
    new Input(String varname);
}

class Output {
    String varname;
    String condition;
    new Output(String varname, String condition);
}

class State {
    String varname;
    new State(String varname);
}

class Wire {
    String condition;
    Input input;
    Ouput output;
    new Wire(Input input, Output output, String condition);
}

Input input1 = new Input("a");
Input input2 = new Input("b");
State state1 = new State("initial");
State state2 = new State("following");
Wire wire12 = new Wire(state1, state2, "b");
Ouput output1 = new Output(c, "state2 & a");

How would the verilog code have to look based on this?

module BasicFsm(
    input clock,
    input reset,
    input a,
    input b,
    output c
);

always @(posedge clock)
//how to continue here?

Answer 1

Some thing like the following would be a good start to an implementation which I think could be derived easily from an input specification.

Before putting anything like this into use you need to test the generated code as well there are many free simulators available for this. There are related questions to free simulators here .

module BasicFsm(
    input      clock,
    input      reset,
    input      a,
    input      b,
    output reg c
);

reg        state;
wire       nexstate;

localparam S_STATE1    = 1'b0; //Could name initial
localparam S_STATE2    = 1'b1; //Could name following

always @(posedge clock or posedge reset) begin
  if(reset) begin
    state <= S_STATE1;
  end
  else begin
    state <= nextstate
  end
end

//Combinatorial nextstate
always @* begin
  case(state) 
    S_STATE1    : 
     if ( b == 1'b1 ) begin
       nextstate = S_STATE2 ; 
     end
     else begin
       nextstate = state ; //Hold state
     end
    S_STATE2    : nextstate = state ; //locked up forever if you get here
    default     : nextstate = S_STATE1;
  endcase
end

//Combinatorial output
always @* begin
  c = (state == S_STATE2) && (a == 1'b1);
end