VHDL if statement error

Question

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux is
port (sel: in std_logic; 
        s0,s1: in std_logic_vector (3 downto 0) ; 
        sout : out std_logic_vector (3 downto 0));  
end mux;

architecture Behavioral of mux is

begin
if sel = '0' then 
    sout <= s0; 
else 
    sout <= s1; 
end if; 

end Behavioral;

-- I'm Trying to make a mux for a four bit serial adder output. If the cin is 0 then it will take the -- sum from the first adder which has cin 0 and if cin is 1 then it will take the sum from the second -- adder which i've fed with cin 1. However there is an error with the if somewhere I can't figure --out. the compiler says error near if else and end if statement

Answer 1

Use the if-else construct within a process with the proper sensitivity list.

`

process(sel)
begin
(
   if sel = '0' then 
      sout <= s0; 
else 
    sout <= s1; 
end if; 
);
end process; 

else use the When Else construct

Answer 2

The if is a sequential statement, so it only goes inside a process . Replace if with when , since that is a concurrent statement thus can be used directly in the architecture:

sout <= s0 when (sel = '0') else s1;