If statement bug in VHDL

Question

I am facing a problem in VHDL via ModelSim. It is an error in my if statement.

if ((s(0) = c(0)) AND (NOT(x1(0)))) THEN 
   I:= (others => '0');
 end if;  

Here is my if statement and the error is: No feasible entries for infix operator "and". But, after I tried to check the program I realized that the problem is with using (not gate). Maybe, there is another way of using it in vhdl. Could anyone help?? Thanks

Answer 1

You have no indication of the type of x1 . It's telling you the expression NOT(x1()))) isn't compatible with any defined AND operator visible by selection (eg context clause specified package visibility).

Try evaluating x1(0) to a value instead of simply using the inversion operator.

for example:

if s(0) = c(0) AND x1(0) = '0' THEN 
    I:= (others => '0');
 end if;  

Should x1 be a type whose element type can be specified with the enumeration value '0'.

(There's a precedence order to operators that says all your parentheses were redundant).