VHDL self checking testbench Syntax error near process

Question

working on a project that requires a self checking test bench which I have written before and had no problem with.

However this one is throwing an error that to me appears to not even be there. The error is right at the bottom and i have written an arrow indicating where it is. If anyone can spot the error that I clearly can't id very much appreciate and know what to look for next time.

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

    ENTITY TestBenchAutomated IS

    generic (m: integer := 3; n: integer := 5; h: integer := 4; DATA_SIZE: integer :=5);

    END TestBenchAutomated;

    ARCHITECTURE behavior OF TestBenchAutomated IS 

         -- Component Declaration for the Unit Under Test (UUT)

         COMPONENT TopLevelM_M
         generic (m: integer := 3; n: integer := 5; h: integer := 4; DATA_SIZE: integer :=5);
         PORT(
                clk : IN  std_logic;
                next_in : IN  std_logic;
                rst_in : IN  std_logic;
                LEDs : OUT  SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0)
              );
         END COMPONENT;


        --Inputs
        signal clk : std_logic := '0';
        signal next_in : std_logic := '0';
        signal rst_in : std_logic := '0';

        --Outputs
        signal LEDs : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);

        -- Clock period definitions
        constant clk_period : time := 10 ns;

     type Vector is record
            LEDs : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);
     end record;

    type VectorArray is array
    (natural range <> ) of Vector;


    constant Vectors : VectorArray := (
    --  LEDs,       
        (X"30"), --48
        (X"f6"),--246
        (X"108"),--264
        (X"FFFFFFD3"),-- -45
        (X"FFFFFF4C"), -- -180
        (X"FFFFFFCF"),-- -49
        (X"ab"), -- 171
        (X"13"), -- 19
        (X"1B"), -- -27
        (X"45"), -- -69
        (X"45"), -- -69
        (X"2d"), -- 45
        (X"122"), -- -290
        (X"56"), -- 86
        (X"f2"), -- 242
        (X"7d"), -- 125
        (X"FFFFFFC9"), -- -55
        (X"115"), -- 277
        (X"FFFFFFE3"), -- -29
        (X"FFFFFF7D")); -- -131


    BEGIN

        -- Instantiate the Unit Under Test (UUT)
        uut: TopLevelM_M PORT MAP (
                 clk => clk,
                 next_in => next_in,
                 rst_in => rst_in,
                 LEDs => LEDs
              );

        -- Clock process definitions
    clk_process :process
    variable  i : integer;
        begin
        for i in Vectors'range loop
            LEDs <= Vectors(i).Test_LEDs;

            wait for clk_period*1;

            wait for 100 ns;
            rst_in <= '1';
            wait for clk_period*3;
            rst_in <= '0';

            for i in 0 to 50 loop --Loops through enough times to cover matrix and more to test what happens

                next_in <= '1';
                wait for clk_period*5;
                next_in <= '0';
                wait for clk_period*1;

                assert LEDs = Vectors(i).Test_LEDs
                report "The answers wrong mate" & integer'image(i)
                severity error;


            end loop;

            wait;

    end process; <------ SAYS THE ERROR IS HERE?!?
END;

Thank you for any help.

Answer 1

At least, before the end process; with the arrow, you must add another:

end loop;

Reasonable indentation makes it easier to spot issues like this.

But, that reveals another issues with assign to constant Vectors : VectorArray :

• The size differs for the elements in constant Vectors : VectorArray ... , since eg X"30" is 8 bits, where X"108" is 12 bits. This can be fixed by resizing.

• If a record contain only a single element, then it is not possible to make unnamed references, not even with () around. This is said explicitly in VHDL-2002 LRM section 7.3.2 Aggregates: "Aggregates containing a single element association must always be specified using named association in order to distinguish them from parenthesized expressions.". This can be fixed with use of others , or named reference.

So the declarations may be updated to:

subtype LEDs_t is signed((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);

type Vector is record
  LEDs : LEDs_t;
end record;

type VectorArray is array (natural range <>) of Vector;

constant Vectors : VectorArray := (
  --  LEDs,
  (LEDs => resize(signed'(X"30"), LEDs_t'length)),         --48
  (LEDs => resize(signed'(X"f6"), LEDs_t'length)),         --246
  (LEDs => resize(signed'(X"108"), LEDs_t'length)),        --264
  (LEDs => resize(signed'(X"FFFFFFD3"), LEDs_t'length)),   -- -45
  (LEDs => resize(signed'(X"FFFFFF4C"), LEDs_t'length)),   -- -180
  (LEDs => resize(signed'(X"FFFFFFCF"), LEDs_t'length)),   -- -49
  (LEDs => resize(signed'(X"ab"), LEDs_t'length)),         -- 171
  (LEDs => resize(signed'(X"13"), LEDs_t'length)),         -- 19
  (LEDs => resize(signed'(X"1B"), LEDs_t'length)),         -- -27
  (LEDs => resize(signed'(X"45"), LEDs_t'length)),         -- -69
  (LEDs => resize(signed'(X"45"), LEDs_t'length)),         -- -69
  (LEDs => resize(signed'(X"2d"), LEDs_t'length)),         -- 45
  (LEDs => resize(signed'(X"122"), LEDs_t'length)),        -- -290
  (LEDs => resize(signed'(X"56"), LEDs_t'length)),         -- 86
  (LEDs => resize(signed'(X"f2"), LEDs_t'length)),         -- 242
  (LEDs => resize(signed'(X"7d"), LEDs_t'length)),         -- 125
  (LEDs => resize(signed'(X"FFFFFFC9"), LEDs_t'length)),   -- -55
  (LEDs => resize(signed'(X"115"), LEDs_t'length)),        -- 277
  (LEDs => resize(signed'(X"FFFFFFE3"), LEDs_t'length)),   -- -29
  (LEDs => resize(signed'(X"FFFFFF7D"), LEDs_t'length)));  -- -131

The explicit signed'(...) is not required in resize, since VHDL will resolve the right resize to use in this case, but I think the explicit type indication makes the intention clear.

As a minor there are also some .Test_LEDs that should be .LEDs .