Makefile target references Makefile

Question

I just discovered this line in a makefile:

%: Makefile

To me, that says "to make any target, you need this makefile" , which strikes me as somewhat obvious.

Is there any situation in which this is not a no-op?

Answer 1

As Etan commented, this will cause every target to be rebuilt whenever the Makefile changes. This is necessary so that anytime you make a change in the build configuration parameters the target will be rebuilt. Otherwise make won't know to rebuild with the new configuration.