Design a Comparator, Logic Design

Question

Design a comparator which has 6 input bits, A2, A1, A0 and B2, B1, B0, and one output bit O. Let A=( A2, A1, A0) and B=(B2, B1, B0), and regard them as unsigned integers. If A>B, O=1; else O=0. Please write down the logic function as your answer. No Verilog code or simulation is needed. Hint: This problem should be solved by analyzing the underlying logic and no K-map is needed. For example, if A2=1 and B2=0, O must be 1 and there is no need to check the values of other input bits. [Ans.] The key is the less significant bits matter only when the more significant bits are the same. So, O = (A2&~B2) | (~(A2^B2)&A1&~B1) | ((~(A2^B2)&(~(A1^B1)&A0&~B0))

I have no idea how they got this answer.

Answer 1

The parantheses doesn't add up. After the last OR sign, there are 5 open parentheses but only 4 close parentheses. Is it supposed to be like this?

(A2 & ~B2) | (~(A2^B2) & A1 & ~B1) | (~(A2^B2) & ~(A1^B1) & A0 & ~B0)