how to use 2 Dimensional array in Verilog

Question

I want to save the data in 2 dimensional Array in verilog syntax. i wrote the code. please any one can check the code and can give me more good idea about how to use 2 dimensional array

  reg [9:0] simple_State [0:10][0:10]

reg [9:0] count,
reg [9:0] index_R; // row
reg [9:0] index_C; //
initial  
begin 
 index_C=0;
 index_R=0 ;
end 

always @ (posedge clock)

simple_State[index_R][index_C]  <= count ;
count    <= count+1   ;
 index_C  <= index_C+1 ;  
if (count== 10 * index_C) 
  index_R<= index_R+1 ;
end

Answer 1

Your code causes index_C and index_R to overflow, and needs a multiplication operation which may be expensive if this desription is meant to be synthesized. simple_State has 11 rows and 11 columns, so a 4 bit for row index and column index is enough. Just do as you would do in any other language: increment column and when it reaches the maximum column value, reset to 0 and increment row value. When this reaches its maximum value, reset it to 0.

reg [9:0] simple_State [0:10][0:10]
reg [9:0] count,
reg [3:0] index_R; // row
reg [3:0] index_C; // column
initial begin 
  index_C = 0;
  index_R = 0 ;
end 

always @ (posedge clock) begin
  simple_State[index_R][index_C]  <= count ;
  count <= count + 1;
  if (index_C == 10) begin
    index_C <= 0;
    if (index_R == 10)
      index_R <= 0;
    else
      index_R <= index_R + 1;
  end
  else
    index_C <= index_C + 1 ;
end

Answer 2

Try to avoid initial block if you are using sequential logic.

reg [9:0] simple_State [0:10][0:10]
reg [9:0] count,
reg [3:0] index_R; // row
reg [3:0] index_C; //
 always @ (posedge clock or negedge rst) begin
   if(!rst) begin
     index_C=0;
     index_R=0 ;
   end
 end
 else
  begin
   simple_State[index_R][index_C]  <= count ;
   count    <= count+1   ;
   index_C  <= index_C+1 ;  
   if (count== 10 * index_C) 
    index_R<= index_R+1 ;
   end
 end