How to pass variables as arguments array in Verilog because in a 48 bit array? I want an array of 23 bits from the first MSB 1. Can someone say me the method or give program for this condition?
For example, if I give an input like:
001010101010111000100010010100100110001101010101
the output should be:
01010101011100010001001.
Basically, you need to perform slicing of packed array.
There can be many methods for doing this, for example streaming operators operators etc.
I've provided a couple of methods here . Using for loops and the -: operator . If you are using system-verilog, then the use of -: operator is preferred.
PS : I still don't get why did you mention two dimensional array .
The technical post webpages of this site follow the CC BY-SA 4.0 protocol. If you need to reprint, please indicate the site URL or the original address.Any question please contact:yoyou2525@163.com.