wire [a-1:0] array [b-1:0];
How can I OR the b array elements and get an a bits result in 1 clk? Thank you
Verilog ways:
reg [a-1:0] or_of_array;
integer i;
always @* begin
or_of_array = array[0];
for(i=1; i<b; i=i+1) begin
or_of_array = or_of_array | array[i];
end
end
SystemVerilog way:
logic [a-1:0] or_of_array;
always_comb begin
or_of_array = 0;
foreach(array[i]) begin
or_of_array |= array[i];
end
end
SystemVerilog also supports wire [a-1:0] wire_or_of_array = array.or();
but may not be supported by all synthesizer.
You can directly use a loop to or each element with previous element.
wire [a-1:0] op;
// Inside an always block
for (int i = 0; i < array.size(); i++)
op = op | array[i];
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