Verilog Code of Dual Port ROM

Question

I want to write verilog code of Dual port ROM in order to access two addresses simultaneously. I write the verilog code for Single port ROM but can't able to et it for Dual port ROM.

This is my verilog code for sinle port ROM.

always @(posedge clk)
 begin
   case(addr)
     3'b000:
     begin
     dout0<=9'b001001001;
     mod70<=001;
     mod50<=001;
     mod30<=001;
     end
     3'b001:
    begin
     dout1<=9'b010010010;
     mod71<=010;
     mod51<=001;
     mod31<=010;
     end
     3'b010:
    begin
     dout2<=9'b100100001;
     mod72<=100;
     mod52<=100;
     mod32<=001;
     end
     3'b011:
    begin
     dout3<=9'b001011010;
     mod73<=001;
     mod53<=011;
     mod33<=010;
     end
     3'b100: 
     begin
     dout4<=9'b010001001;
     mod74<=010;
     mod54<=001;
     mod34<=001;
     end
     3'b101:
    begin
     dout5<=9'b100010010;
     mod75<=100;
     mod55<=010;
     mod35<=010;
     end
     3'b110:
    begin
     dout6<=9'b001100001;
     mod76<=001;
     mod56<=100;
     mod36<=001;
     end
     3'b111:
    begin
     dout7<=9'b010011010;
     mod77<=010;
     mod57<=011;
     mod37<=010;
     end
     endcase
     end

Answer 1

On page 147 of the Xilinx XST user guide you will find examples of RAM and ROM.

They do not provide a dual-port ROM example, but they provide dual-port RAM, and you can omit the write to make it a ROM:

This example is on page 164:

module v_rams_11 (clk, a, dpra, spo, dpo);
    input   clk;               
    input   we;                
    input   [5:0] a;           
    input   [5:0] dpra;        
    output  [15:0] spo;        
    output  [15:0] dpo;        
    reg     [15:0] ram [63:0]; 
    reg     [5:0] read_a;      
    reg     [5:0] read_dpra;   

    always @(posedge clk) begin
        read_a <= a;
        read_dpra <= dpra;
    end

    assign spo = ram[read_a];
    assign dpo = ram[read_dpra];
endmodule