makefile, working fine but running commands even with no changes

Question

I have the following make file. The problem is that even if there are no changes in the two .cpp files, it still run all the commands on prompt. Everything else is working fine.

all: hello1

hello1: make func 

        gcc hellomake.o hellofunc.o -o hello -I.

make: hellomake.c 

        gcc -c hellomake.c

func: hellofunc.c

        gcc -c hellofunc.c

clean:

        rm -rf *o hello

run:

        ./hello 

Answer 1

Here is a sample Makefile that you can modifiy (especially CFLAGS section), and in won't relink

NAME    = xxx
SRCS    = xxx.c
OBJS    = $(SRCS:.c=.o)

CC      = gcc
RM      = rm -rf

CFLAGS  +=  -W -Wall -Wextra
CFLAGS  += -O2
CFLAGS  += -ansi -pedantic
CFLAGS  += -D_FORTIFY_SOURCE=2 -D_GNU_SOURCE

all:    $(NAME)

$(NAME):        $(OBJS)
    $(CC) $(OBJS) -o $(NAME)

clean:
    $(RM) $(OBJS)

fclean: clean
    $(RM) $(NAME)

re:     fclean all

.PHONY: all clean fclean re

.PHONY allow to differentiate eventual file names and rule names

Answer 2

You need to replace the .c to .o in the targets as described below

make: hellomake.o 

        gcc -c hellomake.c

func: hellofunc.o

        gcc -c hellofunc.c