How to create a static library with a Makefile from C source code

Question

I am trying to understand how to create Makefiles. I have the following Makefile:

DESTDIR=../../
PREFIX=../

STATIC=libdemo.a

CC = gcc
CFLAGS = -Wall -Winline -pipe

LDFLAGS = -L../../../lib
LIBS    = -lpthread 

SRC = demo1.c demo2.c

OBJ = $(SRC:.c=.o)

$(STATIC): $(OBJ)
        @echo "[Link (Static)]"
        @ar rcs $(STATIC) $(OBJ)

.c.o:
        @echo [Compile] $<
        @$(CC) -c $(CFLAGS) $< -o $@

clean:
        rm -f $(OBJ) *~ core tags *.bak Makefile.bak libgeniePi.*

.PHONEY:        install
install:        $(TARGET)
        @install -m 0755 libdemo.a  $(DESTDIR)$(PREFIX)/lib

all:
        gcc -g -Wall -o program program.c $(LDFLAGS) $(LIBS)

Which almost does what I want. With make I create a static library out of the the files demo1.c and demo2.c . With make install I place the library in in the correct directory and with make all I finally compile my program that use4s this library which is all fine.

However, the library libdemo.a is executable which I don't think should be like that, right?

And second how can I make that all commands ( make , make install and make all ) will be run in sequence instead of calling them singly?

Answer 1

You chain targets through prerequisites.

To get what you want (and to have make do it by default) you need to add install as a prerequisite of your all target (though we'll be renaming that in a minute) and either replace $(TARGET) in the install prerequisite with $(STATIC) or replace STATIC with TARGET in the assignment and target lines.

Something like this:

DESTDIR=../../
PREFIX=../

STATIC=libdemo.a

CC = gcc
CFLAGS = -Wall -Winline -pipe

LDFLAGS = -L../../../lib
LIBS    = -lpthread 

SRC = demo1.c demo2.c

OBJ = $(SRC:.c=.o)

$(STATIC): $(OBJ)
        @echo "[Link (Static)]"
        @ar rcs $@ $^

.c.o:
        @echo [Compile] $<
        @$(CC) -c $(CFLAGS) $< -o $@

clean:
        rm -f $(OBJ) *~ core tags *.bak Makefile.bak libgeniePi.*

.PHONY: install
install: $(STATIC)
        @install -m 0755 $< $(DESTDIR)$(PREFIX)/lib

all: install
        $(CC) -g -Wall -o program program.c $(LDFLAGS) $(LIBS)

Also notice that I fixed your .PHONEY typo and used $@ , $^ and $< in place of explicit file/variable names in some of the recipes.

That said this will still leave make all rebuilding program from program.c every time you run make all .

To fix that you want to do this:

all: program

program: install program.c
    $(CC) -g -Wall -o $@ program.c $(LDFLAGS) $(LIBS)

instead of your current all target.

Notice though that I couldn't use $< or $^ in that recipe to refer to program.c because of the install prerequisite. Also note that this doesn't actually fix the "always rebuilding" problem (again because of the install prerequisite).

The fix for the rebuilding problem is to not have a phony target at all.

You can either use a real target for the copy instead or you can just let -L do its job and not bother with the local copy of libdemo.a .

all: program.c
    $(CC) -g -Wall -o $@ $< $(LDFLAGS) $(LIBS)

But then again you aren't actually linking to libdemo.a anywhere here so I'm not sure what you are doing with it. (To link with it you would need -ldemo or to list libdemo.a in the linking command.)