How to generate .h header file using makefile and use it in same makefile for compilation of source?

Question

I want to generate a header file abc.h using makefile. And, include this header file in abc.cpp file, which has to be built from same makefile.

I am facing issue that it is not generating .h file before compiling .cpp file. So, i am getting an fatal error for header file not found.

eg:

---

//abc.h
#define VAR "My Name"

---

//abc.cpp
#include "abc.h"

---

So, question is how to write makefile where it generates header file before compiling source file so that i don't get header file inclusion error?

I have created makefile like below but it's not generating file before any other compilation:

---

-include dummy

noinst_LTLIBRARIES = window.la

.PHONY: dummy

dummy:
    @echo "#define VAR "MYNAME" > abc.h

window_la_SOURCES = \
    ../src/abc.cpp 

window_la_CPPFLAGS = \
    -I $(srcdir)/../src/

---

I want to generate abc.h in above makefile before my compilation begins for abc.cpp. So, that i don't get fatal error for header inclusion. Please suggest.

Answer 1

how to write makefile where it generates header file before compiling source file so that i don't get header file inclusion error?

Here is a simple example (assuming that abc.cpp exists, compiles and has main() ):

all: abc

abc.h: Makefile
        @echo "Generating $@"
        @echo "#define VAR \"MYNAME\"" > $@

abc.o: abc.h
abc.cpp: abc.h

abc: abc.o

By default build abc .

The target abc.h is generated by the shell script inside the Makefile and thus depends on the Makefile .

Tell make that the abc.cpp requires the abc.h .

Tell make that abc.o should be rebuild if abc.h changes.

Tell make to build the abc from the abc.o .

Please suggest.

Code generation in the GNU make -based systems is hard and error prone. Though simple example as above seem trivial, on larger projects you might run into various problems for which GNU make offers literally no help in diagnosing or debugging.

My suggestion would be, unless you are prepared to read through the whole of GNU make manual , is to avoid that.

Also, for the cases when you just need a preprocessor define, code generation is really an overkill: most IDEs and build systems already provide way to add preprocessor defines to the project. And many many things in the C/C++ could be reduced to the preprocessor defines.

Answer 2

Makefiles are a simple way to organize code compilation.

You have to create the header file yourself.

Answer 3

My answer includes also my particular problem, that I want to have in a .h file that is included by main.c the hash of the commit for which I am compiling. This is the final version of it, working but only in Git Bash os CMD Line in Windows doesn't know the cut command.

tagver : ver prebuild postbuild
ver.h: Makefile
    @echo "Generating $@"
    @echo #ifndef INC_VER_H_ > inc\$@
    @echo #define INC_VER_H_ >> inc\$@

    $(eval GitTag_Major := $(shell git rev-parse --short=7 HEAD | cut -b 1))
    @echo "Defining major version to: $(GitTag_Major)"
    @echo #define MAJOR_NUMBER 0x$(GitTag_Major) >> inc\$@

    $(eval GitTag_minor := $(shell git rev-parse --short=7 HEAD | cut -b 2-3))
    @echo "Defining minor version to: $(GitTag_minor)"
    @echo #define MINOR_NUMBER 0x$(GitTag_minor) >> inc\$@

    $(eval GitTag_revision := $(shell git rev-parse --short=7 HEAD | cut -b 4-7))
    @echo "Defining revision version to: $(GitTag_revision)"
    @echo #define REVISION_NUMBER 0x$(GitTag_revision) >> inc\$@

    @echo #endif >> inc\$@
ver: ver.h
main.c: ver.h