Exclude source file in compilation using Makefile

Question

Is it possible to exclude a source file in the compilation process using wildcard function in a Makefile?

Like have several source files,

src/foo.cpp
src/bar.cpp
src/...

Then in my makefile I have,

SRC_FILES = $(wildcard src/*.cpp)

But I want to exclude the bar.cpp. Is this possible?

Answer 1

If you're using GNU Make, you can use filter-out :

SRC_FILES := $(wildcard src/*.cpp)
SRC_FILES := $(filter-out src/bar.cpp, $(SRC_FILES))

Or as one line:

SRC_FILES = $(filter-out src/bar.cpp, $(wildcard src/*.cpp))

Answer 2

使用find for it :)

SRC_FILES := $(shell find src/ ! -name "bar.cpp" -name "*.cpp")

Answer 3

你可以使用Makefile subst功能：

 EXCLUDE=$(subst src/bar.cpp,,${SRC_FILES})

Answer 4

The Unix glob pattern src/[!b]*.cpp excludes all src files that start with b.

That only would work, however, if bar.cpp is the only src file that starts with b or if you're willing to rename it to start with a unique character.