Designing FSM's in VHDL using debounce with port map

Question

I made my FSM in VHDL and now I want to use the debounce code with port mapping. Though I have difficulties with the associations. In fact I want to insett the debouncebutton component among the signals that are driving the FSM.

entity myFSM is
    Port ( CLK : in  STD_LOGIC;
           RST : in  STD_LOGIC;
           IN0 : in  STD_LOGIC;
           IN1 : in  STD_LOGIC;
           IN2 : in  STD_LOGIC;
           LED : out  STD_LOGIC_VECTOR (7 downto 0));
end myFSM;

architecture Behavioral of myFSM is
        type state is (A, B, C);
        signal currentS, nextS: state;

        component debouncebutton
            Port ( clk      : in std_logic;     -- connect it to the Clock of the board
           rst      : in std_logic;     -- connect it to the Reset Button of the board          
           input    : in std_logic;     -- connect it to the Push Button of the board
           output   : out std_logic     -- connect it to your circuit
          );
        end component;
begin
myFSM_comb: process (currentS, IN0, IN1, IN2)
begin
    case currentS is
        when A =>   LED <= "11111111";
                        if IN0 = '1' then nextS<=B;
                        elsif IN1 = '1' then nextS<=C;
                        else            nextS<=A;
                        end if;
        when B =>   LED <= "11000011";
                        if IN0 = '1' then nextS<=C;
                        elsif IN1 = '1' then nextS<=A;
                        else nextS<=B;
                        end if;
        when C =>   LED <= "00111100";
                        if IN0 = '1' then nextS<=A;
                        elsif IN1 = '1' then nextS<=B;
                        else nextS<=C;
                        end if;
    end case;
end process;

myFSM_synch: process(CLK,RST)
begin 
    if (RST='1')        then    currentS<=A;
    elsif (rising_edge(CLK)) then currentS<= nextS;
    end if;
end process ;

begin 

db0 : debounce
port map
(
    clk => CLK,
    rst => RST,
    input => IN0,
    output
end Behavioral;

Answer 1

I marked up your code by renaming IN0 to INP0 in the port declaration, declared a signal in the architecture with the name INO to keep from changing every occurrence of the name, removed an extraneous begin and renamed the instantiated component from debounce to debouncebutton to match the component declaration:

library ieee;
use ieee.std_logic_1164.all;

entity myFSM is
    Port ( CLK : in  STD_LOGIC;
           RST : in  STD_LOGIC;
           INP0 : in  STD_LOGIC;  -- name changed
           IN1 : in  STD_LOGIC;
           IN2 : in  STD_LOGIC;
           LED : out  STD_LOGIC_VECTOR (7 downto 0));
end myFSM;

architecture Behavioral of myFSM is
        type state is (A, B, C);
        signal currentS, nextS: state;

        component debouncebutton
            Port ( clk      : in std_logic;     -- connect it to the Clock of the board
           rst      : in std_logic;     -- connect it to the Reset Button of the board          
           input    : in std_logic;     -- connect it to the Push Button of the board
           output   : out std_logic     -- connect it to your circuit
          );
        end component;

        signal IN0: std_logic;  --- added
begin
myFSM_comb: process (currentS, IN0, IN1, IN2)
begin
    case currentS is
        when A =>   LED <= "11111111";
                        if IN0 = '1' then nextS<=B;
                        elsif IN1 = '1' then nextS<=C;
                        else            nextS<=A;
                        end if;
        when B =>   LED <= "11000011";
                        if IN0 = '1' then nextS<=C;
                        elsif IN1 = '1' then nextS<=A;
                        else nextS<=B;
                        end if;
        when C =>   LED <= "00111100";
                        if IN0 = '1' then nextS<=A;
                        elsif IN1 = '1' then nextS<=B;
                        else nextS<=C;
                        end if;
    end case;
end process;

myFSM_synch: process(CLK,RST)
begin 
    if (RST='1')        then    currentS<=A;
    elsif (rising_edge(CLK)) then currentS<= nextS;
    end if;
end process ;

-- begin  -- syntax error you have a begin before process myFSB_comb

db0 : debouncebutton  --- was debounce, needs to match component declaration
port map (
        clk => CLK,
        rst => RST,
        input => INP0,  -- renamed input port
        output=> IN0   --  newly declared signal INO
    );

end Behavioral;

This allowed the new input port INP0 to be associated to the formal input on debouncebutton and the formal output to be connected to the newly declared signal IN0.

You could also go to all the trouble of simply declaring a new signal for the output association and changing instances of the name IN0 other than the port declaration for myFSM.

Your modified code above analyzes. Without creating an entity/architecture pair for debouncebutton it can't be elaborated (or simulated).