I am trying to implement an example of Merge Sort algorithm on VHDL in order to sort 4 128bit numbers.
I am using sequential code. I have a process on which I make comparisons. The process consists of 3 phases which implement the logic behind Merge Sort.
The problem is that I am using a variable count : integer
which counts clock cycles. I want the phases to follow clock cycles.
It seems like the simulation enters the first IF statement (of Phase 1) but does not enter the others so I guess count variable does not update its value.
I have tried several changes but seems like I am missing something here. I know the post is a little big, I would appreciate any help! Thanks!
entity Merge_Sort is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
en : in STD_LOGIC;
In_a : in STD_LOGIC_VECTOR(15 downto 0 ) ;
In_b : in STD_LOGIC_VECTOR(15 downto 0 ) ;
In_c : in STD_LOGIC_VECTOR(15 downto 0 ) ;
In_d : in STD_LOGIC_VECTOR(15 downto 0 ) ;
Sorted_a : out STD_LOGIC_VECTOR(15 downto 0 ) ;
Sorted_b : out STD_LOGIC_VECTOR(15 downto 0 ) ;
Sorted_c : out STD_LOGIC_VECTOR(15 downto 0 ) ;
Sorted_d : out STD_LOGIC_VECTOR(15 downto 0 ) );
end Merge_Sort;
architecture Behavioral of Merge_Sort is
signal temp1a,temp1b,temp1c,temp1d : STD_LOGIC_VECTOR(15 downto 0 ) ;
TYPE arr2 IS ARRAY (0 to 1 ) of STD_LOGIC_VECTOR(15 downto 0) ;
TYPE arr4 IS ARRAY (0 to 3 ) of STD_LOGIC_VECTOR(15 downto 0) ;
signal Array1 , Array2 : arr2 ;
signal mergedArr : arr4 ;
signal temp : std_logic_vector(15 downto 0 ) ;
begin
temp1a <= (others =>'0' ) WHEN reset ='1' else -- Asychronous Resetting
In_a ;
temp1b <= (others =>'0' ) WHEN reset ='1' else
In_b ;
temp1c <= (others =>'0' ) WHEN reset ='1' else -- Asychronous Resetting
In_c ;
temp1d <= (others =>'0' ) WHEN reset ='1' else
In_d ;
Sorted_a <= MergedArr(0) ;
Sorted_b <= MergedArr(1) ;
Sorted_c <= MergedArr(2) ;
Sorted_d <= MergedArr(3) ;
Sort: PROCESS(clk)
variable count : integer range 0 to 3 ;
BEGIN
if(reset ='1' ) then count := 0 ;
end if ;
IF ( clk'EVENT AND clk='1' ) then -- Conditions for process to run
IF (en ='1') then
IF(count =0) THEN -- Phase 1 of sort
if (temp1a<temp1b ) then Array1(0)<=temp1a ; Array1(1) <= temp1b ;
else Array1(1)<=temp1a ; Array1(0) <= temp1b ;
end if ;
if (temp1c<temp1d ) then Array2(0)<=temp1c ;Array2(1) <= temp1d ;
else Array2(1)<=temp1c ; Array2(0) <= temp1d ;
end if ;
count := count +1 ;
END IF ;
IF( count = 1) THEN -- Phase 2 of sort , computing min and max of array
if ( Array1(1) < Array2(1) ) then MergedArr(1) <= Array1(1) ; MergedArr(3) <= Array2(1) ;
else MergedArr(3) <= Array1(1) ; MergedArr(1) <= Array2(1) ;
end if ;
if ( Array1(0) < Array2(0) ) then MergedArr(0) <= Array1(0) ; MergedArr(2) <= Array2(0) ;
else MergedArr(2) <= Array1(0) ; MergedArr(0) <= Array2(0) ;
end if ;
count:= count +1 ;
END IF ;
IF(count =2 ) THEN -- Phase 3 of sort , FINAL
if ( MergedArr(1) > MergedArr(2) ) then
temp<= MergedArr(2 ) ;
MergedArr(2) <= MergedArr(1) ;
MergedArr(1) <= temp ;
end if ;
END IF ;
END IF;
END IF ;
END PROCESS ;
end Behavioral;
The variable count
is updated immediately inside each IF
condition. So, for example, inside the IF(count=0)
, it is incremented to 1. Then it reaches the IF(count=1)
statement, which will of course already be true.
I think really all you need to do is change it to IF ... ELSIF
statements:
IF(count =0) THEN -- Phase 1 of sort
...
ELSIF( count = 1) THEN -- Phase 2 of sort , computing min and max of array
...
ELSIF(count =2 ) THEN -- Phase 3 of sort , FINAL
and I think it will work exactly as you expect.
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