Sequentially consistent memory and atomic registers

Question

Sequential Consistency (for data race free programs, SC-DRF) is the strongest shared memory consistency model provided by modern programming languages (eg, Java or C++11).

In ''Art of Multiprocessor Programming'' the authors (M. Herlihy and N. Shavit) use notion of atomic register in most of the theorems throughout the book.

Is it correct to say that volatile references in Java and atomics with std::memory_order seq_cst in C++ are (indistinguishable from) atomic registers? Is it possible to observe difference between linearizable registers and atomics in C++ if its memory model guarantees sequential consistency on whole space of memory locations marked as std::atomic ?

Answer 1

For the C/C++ case, atomics read or modified with memory_order_seq_cst should give you everything you're looking for (atomic RMW operations, and linearizability is guaranteed.)

For java, volatile gives you linearizability of reads and writes but any serious concurrent code is probably going to want RMW (ie compare and swap) too, so look into the java Atomic package for types that also do compare and swap (I think it is not possible to achieve compare and swap yourself without using these packages or using the synchronized keyword) http://docs.oracle.com/javase/7/docs/api/java/util/concurrent/atomic/package-summary.html