VHDL type conversion for array of arrays in neural network

Question

I'm working with a feed forward neural network developed by David Aledo (See OpenCores project Artificial Neural Network (ANN) ) and I am having trouble with initializing RAM arrays in instances generated by the code.

The code generates layers of the neural network as instances. Each of these instances has block RAM associated with a layer weight matrix. This RAM is represented in the code as an array of arrays of std_logic_vector as shown below:

type ramd_type is array (NumN-1 downto 0) of std_logic_vector(NbitW -1 downto 0);
type layer_ram is array (NumIn-1 downto 0) of ramd_type;

where NumN and NumIN are layer-dependent and NbitW is constant.

What I want to do is to initialize this RAM with a constant. To do this I've created a package containing the following:

type ramd_type0 is array (33 downto 0) of std_logic_vector(NbitW-1 downto 0);
type layer_ram0 is array (26 downto 0) of ramd_type0;
type ramd_type1 is array (4  downto 0) of std_logic_vector(NbitW-1 downto 0);
type layer_ram1 is array (33 downto 0) of ramd_type1;
type ramd_type2 is array (0  downto 0) of std_logic_vector(NbitW-1 downto 0);
type layer_ram2 is array (4  downto 0) of ramd_type2;

constant w0 : layer_ram0 := (others => (others => (others => '0')));
constant w1 : layer_ram1 := (others => (others => (others => '0')));
constant w2 : layer_ram2 := (others => (others => (others => '0')));

Inside the layer Entities I've declared functions which select the constant apropriate to the layer number generic Lnum :

function w_init(LNum : natural) return layer_ram is
begin
  if LNum = 0 then
    return layer_ram(w0);
  elsif LNum = 1 then
    return layer_ram(w1);
  elsif LNum = 2 then
    return layer_ram(w2);
  else
    return layer_ram(w2);
  end if;
end w_init;

Where layer_ram is defined like above.

When analyzing with GHDL I get the following error:

conversion not allowed between not closely related types

In Modelsim I get this one:

Illegal type conversion from work.wb_init.layer_ram0 to layer_ram (array element type difference).

I get that the problem is that according to the simulators the layer_ram and layer_ram0 are not closely related and it's because the array elements have different types ramd and ramd0 . For me this seems to be against the 1993 standard which states that array types are closely related when:

-- For each index position, the index types are either the same or are closely related;

Am I right? How could I initialize these arrays with constants without changing the layer_ram type into an array of std_logic_vectors?

---

edit:

A minimal working example that reproduces my problem can be viewed here: https://gist.github.com/jstefanowicz/e4f43a822cf5dd46c2668bfffa33c66c

library ieee;
use ieee.std_logic_1164.all;

library work;
package wb_init is

    constant NbitW : natural := 18;

    type ramd_type0 is array (1 downto 0) of std_logic_vector(NbitW-1 downto 0);
    type ramd_type1 is array (2  downto 0) of std_logic_vector(NbitW-1 downto 0);

    type layer_ram0 is array (3 downto 0) of ramd_type0;
    type layer_ram1 is array (4 downto 0) of ramd_type1;

    constant w0 : layer_ram0 := (others => (others => (others => '0')));
    constant w1 : layer_ram1 := (others => (others => (others => '0')));

end wb_init ;

--- test_gen:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

library work;
use work.wb_init.all;

entity test_gen is

   generic
   (
      LNum    : natural ;  
      NumN    : natural := 8; 
      NumIn   : natural := 8   
   );

   port
   (
      inputs  : in std_logic_vector(NbitW-1 downto 0);
      outputs : out std_logic_vector(NbitW-1 downto 0) 
   );

end test_gen;

architecture beh of test_gen is

  type ramd_type is array (NumN-1 downto 0) of std_logic_vector(NbitW-1 downto 0); 
  type layer_ram is array (NumIn-1 downto 0) of ramd_type;

  function w_init(LNum : natural) return layer_ram is
  begin
   if LNum = 0 then
     return layer_ram(w0);
   elsif LNum = 1 then
     return layer_ram(w1);
   else
     return layer_ram(w1);
   end if;
  end w_init;

  signal lram  : layer_ram := w_init(LNum); 

begin
  outputs<= inputs;
end beh;

--- test_gen_tb:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

library work;
use work.wb_init.all;

entity test_gen_tb is
end test_gen_tb;

architecture beh of test_gen_tb is

component test_gen is
  generic
  (
     LNum    : natural := 0; 
     NumN    : natural := 64;
     NumIn   : natural := 8  
  );

  port
  (
     inputs  : in std_logic_vector(NbitW-1 downto 0);
     outputs : out std_logic_vector(NbitW-1 downto 0) 
  );

  end component;
  type gen_ar is array (1 downto 0) of natural;
  signal NumN_ar : gen_ar := (2,3);
  signal NumIn_ar : gen_ar := (4,5);
  signal inputs,outputs : std_logic_vector(NbitW-1 downto 0);


begin

  test_gen_inst:
  for i in 0 to 1 generate
  test_gen
  generic map (
    LNum  => i,
    NumN  => NumN_ar(i),
    NumIn => NumIn_ar(i)
  )
  port map (
    inputs  => inputs,
    outputs => outputs
  );  
  end generate;

end beh;

Answer 1

I finally managed to initialize the array of arrays by assigning it element by element in the function winit . Here is a fix for the minimal example posted above: ( https://gist.github.com/jstefanowicz/abad35de9b0a930033e54ed0deeed771 )

library ieee;
use ieee.std_logic_1164.all;

library work;
package wb_init is

    constant NbitW : natural := 18;

    type ramd_type0 is array (1 downto 0) of std_logic_vector(NbitW-1 downto 0);
    type ramd_type1 is array (2  downto 0) of std_logic_vector(NbitW-1 downto 0);

    type layer_ram0 is array (3 downto 0) of ramd_type0;
    type layer_ram1 is array (4 downto 0) of ramd_type1;

    constant w0 : layer_ram0 := (others => (others =>(others =>'0')));
    constant w1 : layer_ram1 := (others => (others =>(others =>'0')));

end wb_init ;

--- test_gen:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

library work;
use work.wb_init.all;

entity test_gen is

   generic
   (
      LNum    : natural ;  
      NumN    : natural ; 
      NumIn   : natural    
   );

   port
   (
      inputs  : in std_logic_vector(17 downto 0);
      outputs : out std_logic_vector(17 downto 0) 
   );

end test_gen;

architecture beh of test_gen is


  type ramd_type is array (NumN-1 downto 0) of std_logic_vector(17 downto 0); 
  type layer_ram is array (NumIn-1 downto 0) of ramd_type;


  function w_init(LNum : natural) return layer_ram is
    variable tmp_arr : layer_ram ;
  begin
    if LNum = 0 then
      for i in 0 to NumIn-1 loop
        for j in 0 to NumN-1 loop
           tmp_arr(i)(j) := w0(i)(j);
        end loop;
     end loop;
    elsif LNum = 1 then
      for i in 0 to NumIn-1 loop
        for j in 0 to NumN-1 loop
           tmp_arr(i)(j) := w1(i)(j);
        end loop;
      end loop;
    else
      for i in 0 to NumIn-1 loop
        for j in 0 to NumN-1 loop
           tmp_arr(i)(j) := (others => '0');
        end loop;
      end loop;
    end if;

    return tmp_arr ;
  end w_init;

  signal lram  : layer_ram := w_init(LNum); 

begin
  outputs<= inputs;
end beh;

--- test_gen_tb:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

--library work;
--use work.wb_init.all;

entity test_gen_tb is
end test_gen_tb;

architecture beh of test_gen_tb is

component test_gen is
  generic
  (
     LNum    : natural ; 
     NumN    : natural ;
     NumIn   : natural   
  );

  port
  (
     inputs  : in std_logic_vector(17 downto 0);
     outputs : out std_logic_vector(17 downto 0) 
  );

  end component;
  type gen_ar is array (1 downto 0) of natural;
  signal NumN_ar : gen_ar := (3,2);
  signal NumIn_ar : gen_ar := (5,4);
  signal inputs,outputs : std_logic_vector(17 downto 0);

begin

  test_gen_inst:
  for i in 0 to 1 generate
  tg:test_gen
  generic map (
    LNum  => i,
    NumN  => NumN_ar(i),
    NumIn => NumIn_ar(i)
  )
  port map (
    inputs  => inputs,
    outputs => outputs
  );  
  end generate;

end beh;