How to change input signal to parameter in systemverilog?

Question

I have an input logic sequence and I would like to convert it to a parameter in order to add it elsewhere in my program.

For example,

module myModule(input logic[7:0] SW, output logic[7:0] LEDR);

     parameter shift = SW;
     assign LEDR = SW[shift + 1: shift];

endmodule

I know that's not correct syntax, I just wanted to get the main idea.

Answer 1

Parameters are by definition compile time constants. That means you can not change their value based on an expression that can change over time.

What you can do is change the way you model so it does not require a parameter. For example , you could write your code as

module myModule(input logic[7:0] SW, output logic[7:0] LEDR);
     assign LEDR = SW[SW +: 2];
endmodule

Answer 2

You cannot convert a variable to parameter. The value of the parameter will be locked after elaborations. A variable will not have a value until simulation.

Part-select (sometimes called range-slice) should do what you need. See Indexing vectors and arrays with +: for more info.

Having SW slice itself does make sense since the resulting value would always be 0. Here is better example:

module myModule(input [8:0] IN, input [2:0] SW, output [1:0] LEDR);
     assign LEDR = IN[SW +: 2];
endmodule