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How to deal with parameter that is array of string in systemverilog?

i have a module with a parameter of array type. which is :

module a # (parameter b [2-1:0] = '{default:"BRAM"})
...
generate
genvar i;
for (i=0; i<2; i=i+1) begin
    sa # (.sb(b[i])) u_sa (
...
endmodule

in the top, the code is

a #(.b("BRAM0","BRAM1")) u_a (
...

but after simulation, i got the value 1'bx in u_a/u_sax/sb ;

how to convey the value "BRAM0" or "BRAM1" to the submodule parameter u_sax/sb ?

thanks for the help~

Why not make parameter b a string:

module a # (parameter string b [2-1:0] = '{default:"BRAM"});

Then you can instantiate module a like this:

  a #(.b('{"BRAM0","BRAM1"})) u_a ();

When asking a question on Stack Overflow, it is helpful to those answering to supply an MCVE :

https://www.edaplayground.com/x/3QMw

module a # (parameter string b [2-1:0] = '{default:"BRAM"});

  initial
    foreach (b[i])
      $display("b[%0d]= %s", i, b[i]);

endmodule

module M;

  a #(.b('{"BRAM0","BRAM1"})) u_a ();

endmodule

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