How to monitor signal in SystemVerilog program block

Question

I'm trying to learn few things about testbenches with SystemVerilog. However I couldn't seem to find a way to monitor DUT signal inside program block

Consider following example. Signal 'dummy' is output of DUT and input to program block. Now I need to monitor 'dummy' in program block to raise a flag 'test' when 'dummy' has particular value.

In general module-driven testbench, I would simply write always @(dummy), but always blocks are not allowed under program. How would I achieve this?

Answer 1

You can write sequential code like this:

program test(input dummy);
  initial begin
    ...
    wait(dummy == <something>);
    ...
    @(posedge dummy);
    ...    
  end
endprogram

Or you could emulate an always construct using a forever loop.

program test(input dummy);
  initial begin
    forever begin
      @(posedge dummy);
      if (dummy == <something>) ...
    end 
  end
endprogram