[英]How to monitor signal in SystemVerilog program block
I'm trying to learn few things about testbenches with SystemVerilog. 我正在尝试使用SystemVerilog了解有关测试平台的一些内容。 However I couldn't seem to find a way to monitor DUT signal inside program block 但是我似乎无法找到监视程序块内部DUT信号的方法
Consider following example. 考虑以下示例。 Signal 'dummy' is output of DUT and input to program block. 信号'dummy'是DUT的输出并输入到程序块。 Now I need to monitor 'dummy' in program block to raise a flag 'test' when 'dummy' has particular value. 现在我需要在程序块中监视'dummy'以在'dummy'具有特定值时引发标记'test'。
In general module-driven testbench, I would simply write always @(dummy), but always blocks are not allowed under program. 在一般模块驱动的测试平台中,我只想写@(虚拟),但程序下不允许使用块。 How would I achieve this? 我怎么做到这一点?
You can write sequential code like this: 您可以像这样编写顺序代码:
program test(input dummy);
initial begin
...
wait(dummy == <something>);
...
@(posedge dummy);
...
end
endprogram
Or you could emulate an always
construct using a forever
loop. 或者您可以使用forever
循环模拟always
构造。
program test(input dummy);
initial begin
forever begin
@(posedge dummy);
if (dummy == <something>) ...
end
end
endprogram
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