RV64 with RV32 instructions support

Question

While going through RISC-V version 2.1 spec, I found in chapter 4 it is mentioned that RV64 should be read in conjunction with RV32. Based on that Following are my doubts.

1. Does RISC-V 64 bit will run 32-bit opcodes?

2. In spec, chapter 9, page 54 instructions are listed with opcodes, does those opcodes belongs to 64-bit too.

3. In spec, chapter 9, page 55 instructions are listed with opcodes, says RV64 is in addition to RV32, so in RV64-bit implementtaion do I need to support RV32I also?

Answer 1

RV64I is a superset of RV32I with the exception of SLLI , SRLI and SRAI . For those instructions the shamt field increased by one bit. In RV32I all instructions operate on 32 bit data. The same instruction will operate on 64 bit data on RV64I. For operations on the lower 32 bit additional instructions are included in RV64I.

A program compiled for RV32I can work on a RV64I machine. It will run without generating an illegal instruction exception but the result will most probably be wrong. So programs compiled for RV32I will only work properly on RV32I machines and programs compiled for RV64I will only work on RV64I machines.

For programs that contain mixed binaries, like bootloader, kernels or firmware, the misa register encodes the register width in the top bits so it is possible to jump to the correct binary with jumps and left shifts. See Priviledged Spec p.15

It is possible for an implementation to support both RV32I and RV64I but this requires support from the system software.