How to include makefile dynamically

Question

Now I have two makefiles, A.mk and B.mk.

A.mk will include B.mk But B.mk is dynamically generated by some command which is executed in A.mk

Here is the pseudo code of A.mk

command to generate B.mk 
include B.mk
compile and link

The question is the include command is something like #include macro in C file. the A.mk try to load the B.mk before the command is executed.

Does anyone can give me some advise?

Many Thanks Jerry

Answer 1

It is possible to make it work like this:

a.mk (at this point, b.mk doesn't exist)

-include b.mk

all:
    @echo foo : $(FOO)

b.mk:
    @echo "FOO=2" > b.mk

With make -f a.mk all we obtain this :

foo : 2

The sign - in front of the include directive allows not to generate a warning if b.mk doesn't exist.

As stated by MadScientist in the comments, you don't need to put B.mk as prerequisite of any target. If make sees it's missing and finds a corresponding target it will automatically build it.