Unable to use enum in systemverilog

Question

I have a design file ALU and another testbench. Here is my code:

parameter WIDHT = 4;

typedef enum logic[1:0] {
   ADD =2'b00,
   AND =2'b01,
   OR = 2'b10,
   XOR = 2'b11
} operation;


module ALU
( 
input logic [WIDHT-1:0] A,B,
input operation op,
output logic [WIDHT-1:0] R,
output logic N,Z,V
);

always_comb
begin
    unique case(op)
            ADD: R = A+B;
            AND: R = A&B;
            OR: R = A|B;
            XOR: R = A^B;
        default : R=0; 
    endcase

    if(R=='b0)
        Z = 1;
    else if (R[WIDHT-1] == 1'b1)
            begin
                if( A[WIDHT-1] == 1'b0 && B[WIDHT-1] == 1'b0)
                    V = 1;
                else
                    N = 1;
            end
    else if (R[WIDHT-1] == 1'b0)
            begin
                if( A[WIDHT-1] == 1'b1 && B[WIDHT-1] == 1'b1)
                    V = 1;
                else
                    begin
                        R=0;
                        Z=0;
                        V=0;
                    end
            end
    end

endmodule: ALU

Here is my testbench:

parameter W = 4;

module ALU_tb;

logic [W-1:0] A,B;
logic [1:0]  op1;
logic [W-1:0] R;
logic N,Z,V;

ALU alu(A,B,op1,R,N,Z,V);

initial
   begin
    $monitor($time," A = %b, B = %b, ope = %b, R = %b, N = %b, Z = %b, V = %b",A,B,op1,R,N,Z,V);

    A =0;
    B=0;

    #10;

    for(A=0; A<2**W ; A++)
        begin   
            for(B=0; B<'d2**W ; B++)
                begin
                    /*for(op =  op.first; op<=op.last; op.next)
                        #10; */
                    for(op1 = 2'b00; op1<=2'b11; op1++)
                        #10;

                    end
           end
   end

endmodule: ALU_tb       

Now, the code compiles successfully but doesn't simulate. It gives me an error saying that I need to assign an enum to the same enum type or one of its value. What is that I am doing wrong? Any suggestions? One thing I found was to use packages and put the typedef enum in it and then import the package in both my design and testbench files. But I am trying to avoid using enum in my testbench. Can someone suggest something?

Answer 1

An enum is a stronger type than most integral types. You need use the package method to make the types assignment compatible.

Another option is making your port a bit-vector, and then casting it to operation type inside your design.