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Systemverilog coverpoint for each element in enum

I am using UVM environment for verification my design. In monitor, I created coverpoints for my design. However, I can not use enums for coverpoint bins.

For each coverpoint, I want to create a bin for each element in enum.

For example, in monitor.sv file

enum bit [7:0]
{
   data_type_0 =8'd1,
   data_type_1 =8'd16,
   data_type_2 =8'd32,
   data_type_3 =8'd64
} data_types;

data_type: coverpoint seq_item.data_type
{
  bins data_type_bins[] = {[data_types.first:data_types.last]};
}

I tried first and last method, but it creates bin for each number between 1 and 64. I don't want that. I want bins for only 1,16,32,64

I have tried it on 4 simulators and do not get the behaviour you get. So, for example this:

    data_type3: coverpoint data_types
    {
    bins data_type_bins[] = {[data_types.first:data_type_2]};
    }

gives me 4 bins. However, why not just use:

data_type2: coverpoint data_types;

and be done with it?


module M;

  enum bit [7:0]
  {
   data_type_0 =8'd1,
   data_type_1 =8'd16,
   data_type_2 =8'd32,
   data_type_3 =8'd64
  } data_types;

  covergroup CG;
    option.per_instance=1;
    data_type1: coverpoint data_types
    {
    bins data_type_bins[] = {[data_types.first:data_types.last]};
    }
    data_type2: coverpoint data_types;
    data_type3: coverpoint data_types
    {
    bins data_type_bins[] = {[data_types.first:data_type_2]};
    }
  endgroup

  CG cg = new;

  initial
    begin
      data_types = data_type_0;
      cg.sample();
      data_types = data_type_2;
      cg.sample();
      $display("cg.data_type1 covereage = %0f", cg.data_type1.get_coverage());
      $display("cg.data_type2 covereage = %0f", cg.data_type2.get_coverage());
      $display("cg.data_type3 covereage = %0f", cg.data_type3.get_coverage());
    end

endmodule

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