Adding variable to a string in systemverilog

Question

I need to generate filenames with variables in the name. Eg. filename needs to be wave_mon[0]_ch0_dat.out The 0 in this string will vary based on a for loop. My code is as below:

for (i=0; i<16; i=i+1) begin
    fname = {"wave_mon[",i,"]_ch",i,"_dat.out"};
    $display("Filename created is %s \n", fname);
    #1us;
end 

The output from this code is always as below. What am I missing that it is not able to print value of i in the string name?

Filename created is wave_mon[]_channel__data.out                                     

Filename created is wave_mon[]_channel__data.out 

Filename created is wave_mon[]_channel__data.out 

Answer 1

Method 1: using $sformat

$sformat(fname,"wave_mon[%0d]_ch%0d_dat.out",i,i);
$display("Filename created is %s \n",fname);

Method 2: using $sformatf

fname={$sformatf("wave_mon[%0d]_ch%0d_dat.out",i,i)};
$display("Filename created is %s \n",fname);

I created code snippet for you to try: https://www.edaplayground.com/x/5uQD

There is more to read about string manipulations in SV here if you wish: https://www.chipverify.com/systemverilog/systemverilog-strings