Use of clock signal in expression not supported

Question

module manenc(inp,clk1,out);
      input inp,clk1;
      output reg out;
      always@(posedge clk1) begin
        out<=inp^clk1;
      end
endmodule

When I run Synthesis for this code in Vivado, it fails and shows: [Synth 8-27] use of clock signal in expression not supported

Also in a different case when I change the always block to always@(posedge clk1 or negedge clk1) it shows : ambiguous clock in event control . What to do?

I'm trying to do manchester encoding, any other methods to achieve that will be appreciated.

Answer 1

Think about this logically, your always block's sensitivity list is triggering on the edge of clk1 . That means the always block's logic is run when clk1 is transitioning . If you were allowed to read the value of clk1 , in theory it would be unpredictable. In reality it is dependent on how the hardware is actually synthesized.

The value of a signal that is transitioning is undefined, so Verilog will not compile something that does not make sense.

For Manchester encoding, what you want to do is latch the output to the negated value of the data you want to send on the rising edge of the clock, and flip it on the falling edge of the clock. Oldfart's comment using the combinational logic assign out = inp ^ clk1; accomplishes this goal, and there is no need to trigger on the edge of a clock signal.

Answer 2

你可以喜欢这个“永远@(*)”