Clock Domain Crossing for Pulse and Level Signal

Question

For pulse we use Pulse-Synchronizer and for Level Signal we use 2-flop synchronizer but what if the signal can be of Pulse or Level behaviour. Is there any way to synchronize that?

Answer 1

Yes, you can but the solution needs to be based on the width of the input pulse relative to the output clock.

When the output clock is very slow, and you have a pulse, you need to add an inline pulse stretcher that operates in the input clock domain. The stretch is defined by the bit width of stretch_out below and "MUST" be greater than one clock on the output clk domain.

reg [3:0] stretch_out;
always @ (posedge inclk)
begin 
   stretch_out <= in_signal ? 4'b1111 : {stretch_out[2:0],1'b0}; 
end

Now you can just use your double flop synchronizer.

reg [1:0] out_sync;
always @ (posedge outclk)
begin 
    out_sync <= {out_sync[0],stretch_out[3]};
end

This should synchronize a level and pulse from a fast domain into a slow domain.

The only issue, is that you will be adding more than just your usual two flop latency.

Answer 2

You could asynchronously set using the signal in the destination domain, synchronize using dual flops, and then detect the rising edge. Should work for both short pulses and long levels.

// Prevent DRC violations if using scan
wire in_signal_n = scan_mode ? 1'b1 : !signal_in;

// Following code creates a flop with both async setb and resetb
reg sig_n_async;
always @ ( posedge outclk or negedge reset_n or negedge in_signal_n)
  if (!reset_n)
    sig_n_async <= 0;
  else if (!in_signal_n)
    sig_n_async <= 1;
  else
    sig_n_async <= 0;


// Synchronizer
reg [1:0] out_sync;
always @ (posedge outclk or negedge reset_n)
  if (!reset_n)
    out_sync <= 0;
  else
    out_sync <= {out_sync[0],sig_n_async};


// Rising edge
reg out_sync_del;
always @ (posedge outclk or negedge reset_n)
  if (!reset_n)
    out_sync_del <= 0;
  else
    out_sync_del <= out_sync[1];

wire signal_out = out_sync[1] & !out_sync_del;