简体   繁体   中英

why does value only update on the next clock pulse

I AM SIMULATING THE CODE BELOW AND WHEN I CHANGE THE I VALID SIGNAL THE data is put into the line only on the next positive edge why does that happen, I have not done any testbench just simulating in vivaldo and forcing this values

在此处输入图像描述

 enter code here
            module lineBuffer(
 input   i_clk,
 input   i_rst,
 input [7:0] i_data,
         input   i_data_valid,
        output [23:0] o_data,
     input i_rd_data
          );

            reg [7:0] line [511:0]; //line buffer
               reg [8:0] wrPntr;
             reg [8:0] rdPntr;

               always @(posedge i_clk)
                   begin
                 if(i_data_valid)
                    line[wrPntr] <= i_data;
                         end

                   always @(posedge i_clk)
                         begin
                         if(i_rst)
                       wrPntr <= 'd0;
                               else if(i_data_valid)
                                wrPntr <= wrPntr + 'd1;
                                          end

               assign o_data ={line[rdPntr],line[rdPntr+1],line[rdPntr+2]};

     always @(posedge i_clk)
           begin
              If(i_rst)
                  rdPntr <= 'd0;
                    else if(i_rd_data)
                     rdPntr <= rdPntr + 'd1;
                          end


                                   endmodule

This is the way a sequence of hardware flops work. You designed such sequences. Here is an example,

  1. at posedge clk you scheduled an update of the wrPntr . It will be stored at the output of the first flop, expressed by wrPntr <= wrPntr + 'd1 .
  2. the next flop, line[wrPntr] <= i_data; will not see the value of wrPntr evaluated before. It will only see it on the next clock cycle.
         +--+      +--+          
         |  |  Q1  |  |
    Q---->  |------>  |----Q2
         +^-+      +^-+
    clk---|---------|

In the above, Q2 will have one clock cycle delay in relation to Q

You should really run a simulation to study behavior of different signals.

The technical post webpages of this site follow the CC BY-SA 4.0 protocol. If you need to reprint, please indicate the site URL or the original address.Any question please contact:yoyou2525@163.com.

 
粤ICP备18138465号  © 2020-2024 STACKOOM.COM