Verilog statement on output port

Question

I am currently designing an instruction decoder for a single cycle RISCV processor. As you can see from the code, I defined all the parts of the r-type instruction to increase the readability. But, in this situation, assign statements gives an error as concurrent assignment or output port connection should be a net type.

How can I assign the part of output port to increase readability?

The code is seen below as:

module instruction_decoder(
input [31:0] instruction_memory,
output [32:0] control_word
);
///////////// CONTROL WORD /////////////
reg bc, jb, pl;
assign bc = control_word[0];
assign jb = control_word[1];
assign pl = control_word[2];
reg mw, rw, md;
assign mw = control_word[3];
assign rw = control_word[4];
assign md = control_word[5];
reg [10:0] fs;
assign fs = control_word[16:6];
reg mb;
assign mb = control_word[17];
reg [4:0] ba, aa, da;
assign ba = control_word[18:22];//rs2
assign aa = control_word[23:27];//rs1
assign da = control_word[28:32];//rd
/////////////////////////////////////////
////////////////////////INSTRUCTION WORD ////////////////////////
/////////R-TYPE/////////
wire [6:0] opcode;
assign opcode = instruction_memory[6:0];
wire [4:0] rd;
assign rd = instruction_memory[11:7];
wire [2:0] funct3;
assign funct3 = instruction_memory[14:12];
wire [4:0] rs1;
assign rs1 = instruction_memory[19:15];
wire [4:0] rs2;
assign rs2 = instruction_memory[24:20];
wire [6:0] funct7;
assign funct7 = instruction_memory[31:25];
/////////////////////////
////////////////////////////////////////////////////////////////

always @(opcode)
begin
case(opcode)
    7'b0110011: //Function-unit operations using registers => R-TYPE INSTRUCTIONS
    begin
    da = rd;
    aa = rs1;
    ba = rs2; 
    mb = 0;
    md = 0;
    rw = 1;
    mw = 0;
    pl = 0;
    end
endcase
end
endmodule

Answer 1

One way to fix the compile errors is to assign individual signals to the control_word net. Change:

reg bc, jb, pl;
assign bc = control_word[0];
assign jb = control_word[1];
assign pl = control_word[2];
reg mw, rw, md;
assign mw = control_word[3];
assign rw = control_word[4];
assign md = control_word[5];
reg [10:0] fs;
assign fs = control_word[16:6];
reg mb;
assign mb = control_word[17];
reg [4:0] ba, aa, da;
assign ba = control_word[18:22];//rs2
assign aa = control_word[23:27];//rs1
assign da = control_word[28:32];//rd

to:

reg bc, jb, pl;
reg mw, rw, md;
reg [10:0] fs;
reg mb;
reg [4:0] ba, aa, da;

assign  control_word[0]     = bc;
assign  control_word[1]     = jb;
assign  control_word[2]     = pl;
assign  control_word[3]     = mw;
assign  control_word[4]     = rw;
assign  control_word[5]     = md;
assign  control_word[16:6]  = fs; 
assign  control_word[17]    = mb;
assign  control_word[22:18] = ba;//rs2
assign  control_word[27:23] = aa;//rs1
assign  control_word[32:28] = da;//rd