Here is the code:
static int __init test3_init(void)
{
uint64_t v,i;
for (i=0;i<10;i++)
{
v= native_x2apic_icr_read();
printk("v=%llx\n",v);
}
return 0;
}
And here is the result:
[ 6658.458919] v=9a557fd8
[ 6658.458925] v=1d
[ 6658.458928] v=17
[ 6658.458930] v=17
[ 6658.458932] v=17
[ 6658.458935] v=17
[ 6658.458937] v=17
[ 6658.458939] v=17
[ 6658.458942] v=17
[ 6658.458944] v=17
Why consecutive reading of the value of this register looks like this. The first two are different, but the remain are the same.
My final goal is to reset APIC_DM_NMI(0x00400) in this register, but if the value is not consistent, what is the point to reset the bit? Someone told me Resetting this bit APIC_DM_NMI can enable NMI from APIC, I don' know, I am totally a newbie. If anyone could provide any information on this MSR, and how to manipulate it correctly will be appreciated.
Thanks.
Somehow I feel that the stable value (ie, 0x17) seems to be a more "normal" value. Can these output repeats? I mean, first two always different, and stable start from 3?
Here is the description of ICR register from Pentium Processor System Architecture (page 395) , I didn't see any cautions about read this reagister.
FYI, here is the ICR register bit specification I found from a lecture notes :
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