[英]Verilog Testbench Errors for Comparator
我是Verilog的新手,我需要為a
等於,小於和大於b
時做一個8位比較器。 這是代碼的內容(不會給我任何錯誤):
module MagnitudeComparator8bit (input signed [7:0]a,
input signed [7:0]b,
output eq,
output lt,
output gt);
assign eq = a == b;
assign lt = a < b;
assign gt = a > b;
endmodule
這就是測試平台的功能,但是當我運行模擬時,我遇到了多個錯誤,但是我不確定哪里出錯了。 有什么幫助嗎?
module MagnitudeComparatorTestbench;
reg [7:0] a, b;
wire eq, lt, gt;
MagnitudeComparator8bit uut(
.a(a),
.b(b),
.eq(eq),
.lt(lt),
.gt(gt)
);
initial begin
$monitor (“%d %b %b %d %d %d”, $time, a, b, eq, lt, gt);
a=8’b11110000;
b=8’b11110000;
#10 a=8’b1001001;
b=8’b10101010;
#10 a=8’b11001100;
b=8’b10101000;
#10 $finish
end
endmodule
錯誤:
testbench.sv:14: error: unmatched character (hex ?)
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: syntax error
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: error: malformed statement
testbench.sv:f: error: unmatched character (hex ?)
testbench.sv:f: error: unmatched character (hex ?)
testbench.sv:f: error: unmatched character (hex ?)
testbench.sv:f: syntax error
testbench.sv:f: error: malformed statement
testbench.sv:10: error: unmatched character (hex ?)
testbench.sv:10: error: unmatched character (hex ?)
testbench.sv:10: error: unmatched character (hex ?)
testbench.sv:10: syntax error
testbench.sv:10: error: malformed statement
testbench.sv:11: error: unmatched character (hex ?)
testbench.sv:11: error: unmatched character (hex ?)
testbench.sv:11: error: unmatched character (hex ?)
testbench.sv:11: syntax error
testbench.sv:11: error: malformed statement
testbench.sv:12: error: unmatched character (hex ?)
testbench.sv:12: error: unmatched character (hex ?)
testbench.sv:12: error: unmatched character (hex ?)
testbench.sv:12: syntax error
testbench.sv:12: error: malformed statement
testbench.sv:13: error: unmatched character (hex ?)
testbench.sv:13: error: unmatched character (hex ?)
testbench.sv:13: error: unmatched character (hex ?)
testbench.sv:13: syntax error
testbench.sv:13: error: malformed statement
testbench.sv:14: error: unmatched character (hex ?)
testbench.sv:14: error: unmatched character (hex ?)
testbench.sv:14: error: unmatched character (hex ?)
testbench.sv:14: syntax error
testbench.sv:14: error: malformed statement
testbench.sv:16: syntax error
Exit code expected: 0, received: 40
您的帖子中有奇怪的引號字符。 在我復制粘貼代碼后,這些錯誤給了我錯誤。 我固定了報價。 復制此代碼:
module MagnitudeComparatorTestbench;
reg [7:0] a, b;
wire eq, lt, gt;
MagnitudeComparator8bit uut(
.a(a),
.b(b),
.eq(eq),
.lt(lt),
.gt(gt)
);
initial begin
$monitor ("%d %b %b %d %d %d", $time, a, b, eq, lt, gt);
a=8'b11110000;
b=8'b11110000;
#10 a=8'b1001001;
b=8'b10101010;
#10 a=8'b11001100;
b=8'b10101000;
#10 $finish;
end
endmodule
在$ finish之后,我還添加了一個半符號。
我嘗試了您的代碼,唯一的問題是$ finish之后缺少分號。 所以#10 $ finish;
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