我的触发器JK总是返回X

Question

I want to write flip flop JK. I wrote it, but when I run it, it always returns x. It's supposed to look like this: pic and test module just for testing

`timescale 1ns / 100ps
module flipflopJK(input j , k , r , s , clk , output q , nq);//nq = not q -- r=rest -- s=set 
    wire w1,w2,w3,w4;//explaine wires in pic in file
    assign w3=q;
    assign w4=nq;
    nand n1(w1,j,clk,nq);
    nand n1(w2,k,clk,w3);
    nand n3(q,r,w1,w4);
    nand n4(nq,s,w2,w3);
endmodule 
module test;
    reg clk,rst,st,a,b;
    wire ck;
    flipflopJK f(.j(a),.k(b),.r(rst),.s(st),.clk(clk),.q(ck),.nq( ));
    initial
    begin
    $monitor("j:%b  k:%b    ck:%b",a,b,ck);
    end
    initial
    begin
        clk = 1'b0;
        rst = 1'b1;
        st=1'b1;
        a=1'b0;b=1'b0;
        #5 a=1'b0;b=1'b1;
        #10 a=1'b1;b=1'b0;
        #15 a=1'b1;b=1'b1;
    end
    always
        #5 clk = ~clk;

endmodule

result after compile it

soroush@soroush:~/Desktop/MadarManteghi/P2$ vvp P2
j:0 k:0 ck:x
j:0 k:1 ck:x
j:1 k:0 ck:x
j:1 k:1 ck:x

Answer 1

I get compile errors. I changed the 2nd n1 instance to n2 .

You need to pulse either st or rst low in your testbench.

initial
begin
    clk = 1'b0;
    rst = 1'b1;
    st=1'b1;
    repeat (5) @(negedge clk);
    st=0;
    repeat (5) @(negedge clk);
    a=1'b0;b=1'b0;
    repeat (5) @(negedge clk);
    a=1'b0;b=1'b1;
    repeat (5) @(negedge clk);
    a=1'b1;b=1'b0;
    repeat (5) @(negedge clk);
    a=1'b1;b=1'b1;
end