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如何为系统verilog生成ctags？

[英]How to generate ctags for system verilog?

原文 2016-11-23 15:54:32 4 2 system-verilog/ ctags/ exuberant-ctags

I want to generate tags file for system verilog. 我想为系统verilog生成tags文件。

I found this really helpful link , and I was able to generate UVM tags file. 我发现这个链接非常有用，我能够生成UVM标签文件。

But my question is about SV. 但我的问题是关于SV。 Since there is no separate sv files, the language is build into the compiler itself, how do i go about creating tags file for that? 由于没有单独的sv文件，语言是构建到编译器本身的，我如何为此创建标记文件？

Thanks in advance. 提前致谢。

2 个解决方案

What was wrong with the link you provided? 您提供的链接出了什么问题？ here are some others 这是其他一些

https://verificationacademy.com/forums/systemverilog/ctags-systemverilog http://hackdut.blogspot.com/2015/03/ctags-and-vim-to-work-with-systemverilog.html https://verificationacademy.com/forums/systemverilog/ctags-systemverilog http://hackdut.blogspot.com/2015/03/ctags-and-vim-to-work-with-systemverilog.html

For improved support of SystemVerilog you can try Universal Ctags , where the Verilog parser was improved to also support SystemVerilog. 为了改进对SystemVerilog的支持，您可以尝试使用Universal Ctags ，其中Verilog解析器已得到改进，也支持SystemVerilog。

I also suggest that you use this Verilog/SystemVerilog Vim Plugin that also includes some basic omni-completion. 我还建议您使用此Verilog / SystemVerilog Vim插件，其中还包括一些基本的全向完成。

Disclaimer: most of this is my work. 免责声明：大部分是我的工作。 Your mileage may vary, but feel free to report issues and ask for improvements. 您的里程可能会有所不同，但随时可以报告问题并要求改进。

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