在系统verilog中生成块

Question

module A#(parameter NUM_PORT=2);

logic port_wire[NUM_PORT];

DUT dut_inst(
  generate
    for(genvar idx=0; idx<NUM_PORT; idx++) begin:num_port
      .port[idx] (port_wire[idx]);
    end:num_port
  endgenerate
);

endmodule

Is the above implementation of generate block is allowed? I mean inside a module instantiation. Sorry if the question is too silly.

Answer 1

No, you can't use a generate construct in the middle of a port list.

But if one of the ports in the list is an array, you can do

module A#(parameter NUM_PORT=2);

logic port_wire[NUM_PORT];

DUT dut_inst(
      .port (port_wire);
);

endmodule
module DUT #(int NP=2)(input logic port[NP]);
...
endmodule