[英]Understanding this T Flip-Flop example?
I'm reading a VHDL book and having trouble understanding an example they gave. 我正在阅读一本VHDL书,无法理解他们给出的示例。
The code given: 给出的代码:
-------------------------------------------------------------------
-- RET T Flip-flop model with active-low asynchronous set input. --
-------------------------------------------------------------------
-- library declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- entity
entity t_ff_s is
port ( T,S,CLK : in std_logic;
Q : out std_logic);
end t_ff_s;
-- entity
architecture my_t_ff_s of t_ff_s is
signal t_tmp : std_logic; -- intermediate signal declaration
begin
tff: process (S,CLK)
begin
if (S = '0') then
Q <= '1';
elsif (rising_edge(CLK)) then
t_tmp <= T XOR t_tmp; -- temp output assignment
end if;
end process tff;
Q <= t_tmp; -- final output assignment
end my_t_ff_s;
What I don't understand is how they assign multiple signals to Q. Outside of the process statement, it's Q <= t_tmp
but inside the process if S='0'
then Q <= '1'
. 我不明白的是它们如何向Q分配多个信号。在流程语句之外,它是Q <= t_tmp
但是在流程内部,如果S='0'
则Q <= '1'
。 How exactly does this work? 这是如何工作的? It looks wrong to me with my limited understanding of VHDL. 我对VHDL的了解有限,这对我来说似乎是错误的。 Basically, this looks the same to me as if writing: 基本上,这对我来说就像写一样:
Q <= '0';
Q <= '1';
Can anyone help me better understand this example better? 谁能帮助我更好地理解这个例子?
You're right to question the example. 您是对示例的质疑。 It's broken. 坏了
Q <= '1';
should be 应该
t_tmp <= '1';
Somebody realised they couldn't read an output, introduced t_tmp and only changed half the code. 有人意识到他们无法读取输出,介绍了t_tmp,只更改了一半代码。
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