I'm reading a VHDL book and having trouble understanding an example they gave.
The code given:
-------------------------------------------------------------------
-- RET T Flip-flop model with active-low asynchronous set input. --
-------------------------------------------------------------------
-- library declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- entity
entity t_ff_s is
port ( T,S,CLK : in std_logic;
Q : out std_logic);
end t_ff_s;
-- entity
architecture my_t_ff_s of t_ff_s is
signal t_tmp : std_logic; -- intermediate signal declaration
begin
tff: process (S,CLK)
begin
if (S = '0') then
Q <= '1';
elsif (rising_edge(CLK)) then
t_tmp <= T XOR t_tmp; -- temp output assignment
end if;
end process tff;
Q <= t_tmp; -- final output assignment
end my_t_ff_s;
What I don't understand is how they assign multiple signals to Q. Outside of the process statement, it's Q <= t_tmp
but inside the process if S='0'
then Q <= '1'
. How exactly does this work? It looks wrong to me with my limited understanding of VHDL. Basically, this looks the same to me as if writing:
Q <= '0';
Q <= '1';
Can anyone help me better understand this example better?
You're right to question the example. It's broken.
Q <= '1';
should be
t_tmp <= '1';
Somebody realised they couldn't read an output, introduced t_tmp and only changed half the code.
The technical post webpages of this site follow the CC BY-SA 4.0 protocol. If you need to reprint, please indicate the site URL or the original address.Any question please contact:yoyou2525@163.com.