implementing a flip-flop with concurrent statement

Question

It is stated in VHDL programming that for combinational circuits, concurrent statements are used while for sequential circuits, both concurrent and sequential statements are applicable. Now the question is:

What will happen if I write a sequential code in a concurrent form? For example, I don't use process and write a flip flop with when..else

architecture x of y is
begin
   q <= '0' when rst=1 else
        d   when (clock'event and clock='1') else
        q;
end;

Is that a correct and synesthesizable code? If it is an incorrect code, what is wrong with that exactly (apart form syntax errors)?

Answer 1

You say: "It is stated in VHDL programming that for combinational circuits, concurrent statements are used while for sequential circuits, both concurrent and sequential statements are applicable.". That is simply not true. You can model both combinational and sequential code using either concurrent or sequential statements.

It is unusual to model sequential logic using concurrent statements. (I say that because I see a lot of other people's code in my job and I almost never see it). However, it is possible. Your code does have a syntax error and a more fundamental error. This modified version of your code synthesises to a rising-edge triggered flip-flop with an asynchronous, active-high reset, as you expected:

q <= '0' when rst='1' else
      d  when clock'event and clock='1';

The syntax error was that you had rst=1 instead of rst='1' . The more fundamental error was that you don't need the else q . This is unnecessary, because signals in VHDL retain the value previously assigned until a new value is assigned. Therefore, in VHDL code modelling sequential logic, it is never necessary to write q <= q (or its equivalent). In your case, in the MCVE I constructed q was an output and so your else q gave a syntax error because you cannot read outputs.

Here's the MCVE:

library IEEE;
use IEEE.std_logic_1164.all;

entity concurrent_flop is
  port (clock, rst, d : in  std_logic;
        q             : out std_logic);
end entity concurrent_flop;

architecture concurrent_flop of concurrent_flop is
begin
   q <= '0' when rst='1' else
         d  when clock'event and clock='1';
end architecture concurrent_flop;

I wrote an MCVE to check what I was about to say was correct. You could have done the same. Doing so is a great way of learning VHDL. EDA Playground is often a good place to try things out (shameless plug), but was no good in this case, because one cannot synthesise VHDL on EDA Playground.