VHDL flip-flop reset different than 0

Question

is any possibility to reset flip-flop vector to different value than all 0? something like:

PROCESS (clk)
    BEGIN
        IF RISING_EDGE(clk) THEN
            IF rst = '1' THEN
                ff <= INPUT_VALUE;
...

This don't survive synthesis. I want to get the value to ff only when resetting, then I'm changing it - it works as a counter with first value set from input.

Answer 1

How about implementing a normal reset and then use load signal to set the counter to something else? This to me would be the standard way.

Answer 2

The following is an amusing answer that would actually work:

1) Determine the bit pattern of the value that it should be initialized to.

2) For every bit that should be a 1, put a not gate on that line before and after the flip-flop.

Now the initial state after the reset pin is the state you want.