Variable initialization in vhdl

Question

I am using Xilinx Isim for vhdl simulation. i have intialized a variable like (signal q: std_logic_vector(15 downto 0):="0000000000000000";) . But when it comes to simulation that particular value is not initialized. its showing undefined('U') . I have to use that value in feedback. so the values depending on it are also undefined('U') . And one more thing, if initialize the signal is get synthesized? what happens when I dump it in to an FPGA? please tell me the solution

Answer 1

The initialisation expression will work in ISIM, as well as for synthesis with XST. What you are seeing suggests there is a driver on that signal which is uninitialised or not properly reset. Find and check all the drivers on that signal - reading the ISIM documentation for its "drivers" command may help you in this task.