Precedence of initialized port/signal assigned to port in VHDL

Question

I have a question regarding initialization in VHDL. If I have an entity output port that is initialized to a certain value, but is assigned to a signal that is initialized to a different value, what initial value will the output assume. I mean a situation like the following:

entity TEST_ENTITY is
    Port (port0    : out    STD_LOGIC    := '0');
end TEST_ENTITY;

architecture Behavioral of TEST_ENTITY is
    signal signal0    : STD_LOGIC    := '1';

begin

    port0    <= signal0;
end Behavioral;

I would assume that the initialization value of the signal will take precedence. Is this correct?

Answer 1

There is no precedence here. Signal assignments take at least one delta cycle to pass. So at time 0, port0 will be '0' and signal0 will be '1' . Port0 will become '1' after 1 delta cycle has elapsed.