D flip-flop synthesizable

Question

I want to make a D ff with a little delay on the reset, D will always be '1', clk will be controlled by a switch(it will give a command for a specific floor on an elevator) and count_aux will be a 1Hz clock, but when I try to synthesize it shows me this error "ERROR:Xst:1534 - Sequential logic for node appears to be controlled by multiple clocks.". I don't want to clk to be understood as a clock, since it will be just a switch. How can I do that?

library ieee;  
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity D_FF is
port ( D: in std_logic;
clk: in std_logic;
count_aux: in std_logic;
reset: in std_logic;
Q: out std_logic:='0'
); 
end D_FF;    

architecture a1 of D_FF is
signal i: std_logic_vector(3 downto 0):="0000";
begin
proc: process (D,clk,reset)


begin  

    if (reset='1') then 
        if(count_aux'event and count_aux='1') then i<=i+1;
            if (i="0001") then 
        q<='0';
        i<="0000";
            end if;
        end if;
    elsif (clk'event and clk='1') then 
        q<=d;   
    end if;  
    end process proc;
end a1;

Answer 1

You are using clk as a clock in the process, so it will be a clock ;) But the weird thing for the synthesis is that you want to have a clocked flipflop (sequential element or regeister or what ever) but yet you also include combinatorial logic into the reset. So it has no idea what to synthesize since it has no component in the library for this logic.

So my advise is to keep the sequential and combinatorial logic separate. Sequential logic will have only clk and reset in the sensitivity list and have the code structure of:

process(clk, reset)
begin
  if reset = 1 then
    foobar <= '0';
  elsif rising_edge(clk) then
    foobar <= foo + bar;
  end if;
end process;