I have a flip-flop that I need to enable for only one clock cycle. What is the standard practice for single-cycle enable signal in these kind of situations?
Thanks in advance
Flip-flop that is only enabled a single cycle after reset is shown below; all signals are std_logic:
process (clk, rst) is
begin
if rst = '1' then
fired <= '0';
elsif rising_edge(clk) then
if fired = '0' then
q <= d;
fired <= '1';
end if;
end if;
end process;
The technical post webpages of this site follow the CC BY-SA 4.0 protocol. If you need to reprint, please indicate the site URL or the original address.Any question please contact:yoyou2525@163.com.