Populate Makefile Variable with For Loop

Question

I have the files args.cpp/h , output.cpp/h , and computation.cpp/h . I want to use both their object files and their header files as dependencies.

I'm trying to minimize code duplication by creating a makefile variable with just their base names then populating two other makefile variables with their object file names and header file names, respectively.

Here is what I'm trying so far, with no results:

BASES = args output computation
OBJS =
CODE =
for base in $(BASES); do \
    OBJS += $$base.o ; \
    CODE += $$base.h ; \
done;

Am I even approaching this the right way? If so, how do I fix the for loop? If not, what makefile approach should I use to eliminate the code duplication?

Answer 1

That's a mix of shell and make and that can't work that way. You can do something along those lines if you really wanted but there's no reason to do it that way.

BASES = args output computation
OBJS = $(addsuffix .o,$(BASES))
CODE = $(addsuffix .h,$(BASES))

or

CODE = args.h output.h computation.h
OBJS = $(CODE:.h=.o)