How to support architecture reuse with minor differences

Question

I need some hints about VHDL. I'm pretty new to it so be kind.

I've written a module and I've registered the output (it's a Carry Save Adder - CSA). I've used this module in some part of my design.

Now I've to use the same module, but I need to remove the output register (I need to use that in a combinational way). I know that I could copy and paste the VHDL code and use a different entity, but in my opinion it's a little bit inelegant.

I thought to use a generic parameter, but I don't know where to start. Can someone give me a hint?

Answer 1

Yes, add a registered output generic to the architecture. If this is true, implement the registered output. If it's false, connect the output to what would have been the input to the register. You can then instantiate it in the two different locations with the generic set differently.

This code is completely untested (not compiled even), but hopefully you get the idea.

GEN_REG : if REG_OUTPUT = true generate
    p_output : process is
    begin  -- process p_output
        wait until clk'event and clk = '1';
        Q <= Q_internal;
    end process p_output;
end generate GEN_REG;

GEN_WIRE : if REG_OUTPUT = false generate
    Q <= Q_internal;
end generate GEN_WIRE;