Implementation of FENCE in the RISC-V Rocket processor

Question

What does the FENCE instruction do in the Rocket CPU? I tried going through the fpga source but could not find it.

Aside, where is the write buffer implemented? I might get my answer there :)

Answer 1

[Rocket's source code] (Rocket is a 5-stage processor).

Instructions that require a fence , like FENCE or certain atomic operations, will be stalled in the Decode Stage until the cache tells the control logic that a fence operation may proceed (ie, the cache is now "ordered"). The cache does this via the "ordered" signal. The data-cache would not be ordered if, for example, it had an outstanding cache miss it is waiting on.

The best place to look is ctrl.scala , which contains the instructions and their control signals. The (non-blocking) data cache's code can be found in nbdcache.scala .

I believe the writeback unit governs the writing back of store-data, but this is a very complex, high-performance cache with AMO and ECC support, so do not expect it to match much simpler cache designs where a write-buffer would conceptually be drawn as being between the processor and the cache.