Verilog Input Text Parsing using Python Regex

Question

so I'm trying to parse some verilog files using python. I need to find inputs, outputs, etc. However, in some files, some inputs and outputs have multiple bitwidths, like so:

input read_enable,
input [WIDTH-1 : 0] write_data,

I'm using regular expressions to go through the text file one line at a time, so right now if the line contains the word input I run:

input_mod = re.search(r'(.*?)input\s(.*?)(\s?)(.*?),', line)
inputs.append(input_mod.group(4)) 

Where inputs is a list I declared earlier. I need to extract the input's name. I'm rather new to python and regex's so I'm not sure if this will work, is this correct? Is there a better way to do this?

Note: I know doxygen exists, but my boss wants a native function in their python class.

Answer 1

.*?\binput\b.*? (\S+),

You can use this. inputs.append(input_mod.group(1)) This will take care of everything in between input and the last non space string before , .See demo.

https://regex101.com/r/nS2lT4/4#python