cyclic shift using d flip flop vhdl

Question

I am trying to design a shiftier using d flip flop as a component.. The flip flop works fine.. but the shifter output remains undefined ,, how should I fix it? this is the shiftier code

entity cyclicSR is -- 3-bit cyclic shift register
 port (CLK: in bit; Qout: out bit_vector(1 to 3) ) ;
 end cyclicSR;
 architecture cyclicSR3 of cyclicSR is
 component DFF
 port (D, CLK: in bit; Q: out bit);
 end component;
 signal Q1, Q2, Q3: bit;
 begin
 FF1: DFF port map (Q3, CLK, Q1);
 FF2: DFF port map (Q1, CLK, Q2);
 FF3: DFF port map (Q2, CLK, Q3);
 Qout <= Q1&Q2&Q3;
 end cyclicSR3;

Should I assign a value to q3?? how can i do that?

Answer 1

While you didn't provide a Minimal, Complete, and Verifiable example the problem is visible in your code example.

You need to provide an initial value or 'set' to at least one flipflop. Otherwise it happily shifts all zeros cyclically - the default value for type BIT.

Alternatively you could jam an input into say the first flip flop when all three are 0:

architecture jam of cyclicsr is

    component dff is
        port (
             d, clk: in  bit; 
             q:      out bit
        );
    end component;

     component or2 is 
         port (
             a:     in  bit;
             b:     in  bit;
             y:     out bit
         );
     end component;

     component nor3 is
         port (
             a:     in  bit;
             b:     in  bit;
             c:     in  bit;
             y:     out bit
         );
     end component;

     signal q1, q2, q3: bit;

     signal inp:        bit;   -- added
     signal all_zero:   bit;

begin

 ff1: dff port map (inp, clk, q1);  -- was q3
 ff2: dff port map (q1, clk, q2);
 ff3: dff port map (q2, clk, q3);

     qout <= q1 & q2 & q3;

orgate:
    or2 
        port map (
            a => all_zero,
            b => q3,
            y => inp
        );
allzero:
    nor3
        port map (
            a => q1,
            b => q2,
            c => q3,
            y => all_zero
        );

end architecture;

And that gives:

And note you can set any pattern you want with an initial value or with the a single inverter turn the shift register into a Johnson counter .