VHDL, D-type asynchronous flip flop

Question

I just started learning vhdl code and i wrote this code for a D type asynch flip flop. How should i modify my code so that it has a second D-type, with the input to the second being fed from the output of the first?.

library ieee;
use ieee.std_logic_1164.all;

entity FLIPFLOP is
port ( 
  clk : in  std_logic ;
  clr : in  std_logic ;
  D   : in  std_logic ;
  Q   : out  std_logic
  );
end FLIPFLOP;

architecture behav of FLIPFLOP is
begin
process (clk,clr,D)
begin
if clr = '1' then
Q<= '0';
elsif rising_edge (clk) then
Q<= D;
end if;
end process;
end behav;

Answer 1

I think you need to write a top level VHDL file which uses you DFF architecture:

entity top is
port (
  clk: in std_logic;
  clr: in std_logic;
  some_input_signal: in std_logic;
  some_output_signal: out std_logic
);
end top;

architecture rtl of top is
  signal x: std_logic;
begin
  e1: entity work.FLIPFLOP
  port map (
    clk => clk,
    clr => clr,
    D => some_input_signal,
    Q => x );

  e2: entity work.FLIPFLOP
  port map (
    clk => clk,
    clr => clr,
    D => x,
    Q => some_output_signal );
end;

x is the signal which is outputed by the first DFF and inputed to the second DFF.